Open bit line dram with ultra thin body transistors

ABSTRACT

Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. The pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. In each memory cell a single crystalline vertical transistor is formed along side of the pillar. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions, and a gate opposing the vertical body region and separated therefrom by a gate oxide. A plurality of buried bit lines are formed of single crystalline semiconductor material and disposed below the pillars in the array memory cells for interconnecting with the first contact layer of column adjacent pillars in the array of memory cells. Also, a plurality of word lines are included. Each word line is disposed orthogonally to the plurality of buried bit lines in a trench between rows of the pillars for addressing gates of the single crystalline vertical transistors that are adjacent to the trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to the following co-pending, commonlyassigned U.S. patent applications: “Folded Bit Line DRAM with Ultra ThinBody Transistors,” attorney docket no. 1303.004US1, Ser. No. ______,“Programmable Logic Arrays with Ultra Thin Body Transistors,” attorneydocket no. 1303.007US1, Ser. No. ______, “Memory Address and DecodeCircuits with Ultra Thin Body Transistors,” attorney docket no.1303.006US1, Ser. No. ______,“Programmable Memory Address and DecodeCircuits with Ultra Thin Body Transistors,” attorney docket no.1303.008US1, Ser. No. ______, “In Service Programmable Logic Arrays withUltra Thin Body Transistors,” attorney docket no. 1303.009US1, Ser. No.______, and “Flash Memory with Ultra Thin Vertical Body Transistors,”attorney docket no. 1303.003US1, Ser. No. ______, which are filed oneven date herewith and each of which disclosure is herein incorporatedby reference.

FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuits,and in particular to open bit line DRAM with ultra thin bodytransistors.

BACKGROUND OF THE INVENTION

[0003] Semiconductor memories, such as dynamic random access memories(DRAMs), are widely used in computer systems for storing data. A DRAMmemory cell typically includes an access field-effect transistor (FET)and a storage capacitor. The access FET allows the transfer of datacharges to and from the storage capacitor during reading and writingoperations. The data charges on the storage capacitor are periodicallyrefreshed during a refresh operation.

[0004] Memory density is typically limited by a minimum lithographicfeature size (F) that is imposed by lithographic processes used duringfabrication. For example, the present generation of high density dynamicrandom access memories (DRAMs), which are capable of storing 256Megabits of data, require an area of 8F² per bit of data. There is aneed in the art to provide even higher density memories in order tofurther increase data storage capacity and reduce manufacturing costs.Increasing the data storage capacity of semiconductor memories requiresa reduction in the size of the access FET and storage capacitor of eachmemory cell. However, other factors, such as subthreshold leakagecurrents and alpha-particle induced soft errors, require that largerstorage capacitors be used. Thus, there is a need in the art to increasememory density while allowing the use of storage capacitors that providesufficient immunity to leakage currents and soft errors. There is also aneed in the broader integrated circuit art for dense structures andfabrication techniques.

[0005] As the density requirements become higher and higher in gigabitDRAMs and beyond, it becomes more and more crucial to minimize cellarea. One possible DRAM architecture is the open bit line structure.

[0006] The continuous scaling, however, of MOSFET technology to the deepsubmicron region where channel lengths are less than 0.1 micron, 100 nm,or 1000 A causes significant problems in the conventional transistorstructures. As shown in FIG. 1, junction depths should be much less thanthe channel length of 1000 A, or this implies junction depths of a fewhundred Angstroms. Such shallow junctions are difficult to form byconventional implantation and diffusion techniques. Extremely highlevels of channel doping are required to suppress short-channel effectssuch as drain-induced barrier lowering; threshold voltage roll off, andsubthreshold conduction. Sub-threshold conduction is particularlyproblematic in DRAM technology as it reduces the charge storageretention time on the capacitor cells. These extremely high dopinglevels result in increased leakage and reduced carrier mobility. Thusmaking the channel shorter to improve performance is negated by lowercarrier mobility.

[0007] Therefore, there is a need in the art to provide improved memorydensities while avoiding the deleterious effects of short-channeleffects such as drain-induced barrier lowering; threshold voltage rolloff, and sub-threshold conduction, increased leakage and reduced carriermobility. At the same time charge storage retention time must bemaintained.

SUMMARY OF THE INVENTION

[0008] The above mentioned problems with semiconductor memories andother problems are addressed by the present invention and will beunderstood by reading and studying the following specification. Systemsand methods are provided for transistors with ultra thin bodies, ortransistors where the surface space charge region scales down as othertransistor dimensions scale down.

[0009] In one embodiment of the present invention, an open bit line DRAMdevice is provided. The open bit line DRAM device includes an array ofmemory cells. Each memory cell in the array of memory cells includes apillar extending outwardly from a semiconductor substrate. The pillarincludes a single crystalline first contact layer and a singlecrystalline second contact layer separated by an oxide layer. In eachmemory cell a single crystalline vertical transistor is formed alongside of the pillar. The single crystalline vertical transistor includesan ultra thin single crystalline vertical first source/drain regioncoupled to the first contact layer, an ultra thin single crystallinevertical second source/drain region coupled to the second contact layer,an ultra thin single crystalline vertical body region which opposes theoxide layer and couples the first and the second source/drain regions,and a gate opposing the vertical body region and separated therefrom bya gate oxide. A plurality of buried bit lines are formed of singlecrystalline semiconductor material and disposed below the pillars in thearray memory cells for interconnecting with the first contact layer ofcolumn adjacent pillars in the array of memory cells. Also, a pluralityof word lines are included. Each word line is disposed orthogonally tothe plurality of buried bit lines in a trench between rows of thepillars for addressing gates of the single crystalline verticaltransistors that are adjacent to the trench.

[0010] The invention also provides a method of fabricating an open bitline DRAM device. The method includes forming an array of memory cells.According to the teachings of the present invention forming each memorycell in the array of memory cells includes forming a pillar extendingoutwardly from a semiconductor substrate. Forming the pillar includesforming a single crystalline first contact layer of a first conductivitytype and forming a single crystalline second contact layer of the firstconductivity type vertically separated by an oxide layer.

[0011] Forming each memory cell in the array of memory cells furtherincludes forming a single crystalline vertical transistor along side ofthe pillar. Forming the single crystalline vertical transistor includesdepositing a lightly doped polysilicon layer of a second conductivitytype over the pillar and directionally etching the polysilicon layer ofthe second conductivity type to leave only on sidewalls of the pillars.Forming the single crystalline vertical transistor includes annealingthe pillar such that the lightly doped polysilicon layer of the secondconductivity type recrystallizes and lateral epitaxial solid phaseregrowth occurs vertically to form a single crystalline verticallyoriented material of the second conductivity type. According to theteachings of the present invention, annealing causes the singlecrystalline first and second contact layers of a first conductivity typeto seed a growth of single crystalline material of the firstconductivity type into the lightly doped polysilicon layer of the secondtype to form vertically oriented first and second source/drain regionsof the first conductivity type separated by the now single crystallinevertically oriented material of the second conductivity type. Formingthe single crystalline vertical transistor further includes forming agate opposing the single crystalline vertically oriented material of thesecond conductivity type which is separated therefrom by a gate oxide.

[0012] Forming each memory cell in the array of memory cells furtherincludes forming a plurality of buried bit lines of single crystallinesemiconductor material which are disposed below the pillars in the arraymemory cells such that each one of the plurality of buried bit linescouples to the first contact layer of column adjacent pillars in thearray of memory cells. The method further includes forming a pluralityof word lines disposed orthogonally to the plurality of buried bitlines. Forming the plurality of word lines includes forming each one ofthe plurality of wordlines in a trench between rows of the pillars foraddressing gates of the single crystalline vertical transistors that areadjacent to the trench.

[0013] These and other embodiments, aspects, advantages, and features ofthe present invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is an illustration of a convention MOSFET transistorillustrating the shortcomings of such conventional MOSFETs as continuousscaling occurs to the deep sub-micron region where channel lengths areless than 0.1 micron, 100 nm, or 100 Å.

[0015]FIG. 2A is a diagram illustrating generally one embodiment of anopen bit line DRAM with vertical ultra thin body transistors accordingto the teachings of the present invention.

[0016]FIG. 2B illustrates an embodiment of the present invention for anopen bit line architecture practiced having a single wordline/gate pervertical ultra thin body transistors formed on opposing sides of pillarsaccording to the teachings of the present invention.

[0017]FIG. 3 is a diagram illustrating a vertical ultra thin bodytransistor formed along side of a pillar according to the teachings ofthe present invention.

[0018]FIG. 4A is a perspective view illustrating generally oneembodiment of a portion of an open bit line memory according to thepresent invention.

[0019]FIG. 4B is a top view of FIG. 4A illustrating generally pillarsincluding the ultra thin single crystalline vertical transistors.

[0020]FIG. 4C is a perspective view illustrating another embodiment of aportion of an open bit line memory array according to the presentinvention.

[0021]FIG. 4D is a cross sectional view taken along cut-line 4D-4D ofFIG. 4C illustrating generally pillars including the ultra thin singlecrystalline vertical transistors according to the teachings of thepresent invention.

[0022] FIGS. 5A-5C illustrate an initial process sequence which forforming pillars along side of which vertical ultra thin body transistorscan later be formed as part of forming an open bit line DRAM accordingto the teachings of the present invention.

[0023] FIGS. 6A-6C illustrate that the above techniques described inconnection with FIGS. 5A-5C can be implemented with a bulk CMOStechnology or a silicon on insulator (SOI) technology.

[0024] FIGS. 7A-7D illustrate a process sequence continuing from thepillar formation embodiments provided in FIGS. 5A-6C to form verticalultra thin body transistors along side of the pillars.

[0025] FIGS. 8A-8C illustrate a process sequence for forming ahorizontal gate structure embodiment, referred to herein as horizontalreplacement gates, in connection with the present invention.

[0026] FIGS. 9A-9D illustrate a process sequence for forming a verticalgate structure embodiment, in connection with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following detailed description of the invention, referenceis made to the accompanying drawings which form a part hereof, and inwhich is shown, by way of illustration, specific embodiments in whichthe invention may be practiced. The embodiments are intended to describeaspects of the invention in sufficient detail to enable those skilled inthe art to practice the invention. Other embodiments may be utilized andchanges may be made without departing from the scope of the presentinvention. In the following description, the terms wafer and substrateare interchangeably used to refer generally to any structure on whichintegrated circuits are formed, and also to such structures duringvarious stages of integrated circuit fabrication. Both terms includedoped and undoped semiconductors, epitaxial layers of a semiconductor ona supporting semiconductor or insulating material, combinations of suchlayers, as well as other such structures that are known in the art. Thefollowing detailed description is not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims.

[0028]FIG. 2A is a diagram illustrating generally one embodiment of anopen bit line DRAM with vertical ultra thin body transistors accordingto the teachings of the present invention. In general, FIG. 2A shows anintegrated circuit 200, such as a semiconductor memory device,incorporating an array of memory cells provided by the invention. Asshown in FIG. 2A, circuit 200 includes memory cell arrays 210, such as210A and 210B. Each array 210 includes M rows and N columns of memorycells 212.

[0029] In the embodiment of FIG. 2A, each memory cell includes atransfer device, such as n-channel cell access field-effect transistor(FET) 230. More particularly, access FET 230 includes at least one, butmay include two, gates for controlling conduction between the accessFET's 230 first and second source/drain terminals.

[0030] Access FET 230 is coupled at a second source/drain terminal to astorage node of a storage capacitor 232. The other terminal of storagecapacitor 232 is coupled to a reference voltage such as a ground voltageVSS. Each of the M rows includes one of word lines WL0, WL1 . . . WLm-1,WLm which serve as or are coupled to a first gate of access FETs 230. Inthe embodiment shown in FIG. 2A, each of the M rows also includes one ofword lines R0, R2, . . . ,Rm-1, Rm coupled to a second gate of accessFETs 230 in memory cells 212. As one of ordinary skill in the art willunderstand upon reading this disclosure, two wordlines per access FET230 are not required to practice the invention, but rather represent oneembodiment for the same. The invention may be practiced having a singlewordline/gate per access FET 230 and the same is illustrated in FIG. 2B.The invention is not so limited. The term wordline includes anyinterconnection line for controlling conduction between the first andsecond source/drain terminals of access FETs 230. According to theteachings of the present invention, and as explained in more detailbelow, access FETs 230 include vertical ultra thin body transistors 230.

[0031] Each of the N columns includes one of bit lines BL0, BL1 . . .BLn-1, Bln. Bit lines BL0-BLn are used to write to and read data frommemory cells 212. Word lines WL0-WLm and RO-RM are used to activateaccess FETs 230 to access a particular row of memory cells 212 that isto be written or read. As shown in FIGS. 2A and 2B, addressing circuitryis also included. For example, address buffer 214 controls columndecoders 218, which also include sense amplifiers and input/outputcircuitry that is coupled to bit lines BL0-BLn. Address buffer 214 alsocontrols row decoders 216. Row decoders 216 and column decoders 218selectably access memory cells 212 in response to address signals thatare provided on address lines 220 during read and write operations. Theaddress signals are typically provided by an external controller such asa microprocessor or other memory controller. Each of memory cells 212has a substantially identical structure, and accordingly, only onememory cell 212 structure is described herein. The same are described inmore detail in connection with FIG. 3.

[0032] In one example mode of operation, circuit 200 receives an addressof a particular memory cell 212 at address buffer 214. Address buffer214 identifies one of the word lines WL0-WLm of the particular memorycell 212 to row decoder 216. Row decoder 216 selectively activates theparticular word line WL0-WLm to activate access FETs 230 of each memorycell 212 that is connected to the selected word line WL0-WLm. Columndecoder 218 selects the one of bit lines BL0-BLn of the particularlyaddressed memory cell 212. For a write operation, data received byinput/output circuitry is coupled to the one of bit lines BL0-BLn andthrough the access FET 230 to charge or discharge the storage capacitor232 of the selected memory cell 212 to represent binary data. For a readoperation, data stored in the selected memory cell 212, as representedby the charge on its storage capacitor 232, is coupled to the one of bitlines BL0-BLn, amplified, and a corresponding voltage level is providedto the input/output circuits.

[0033] According to one aspect of the invention, each of the first andsecond gates of access FET 230 is capable of controlling the conductionbetween its first and second source/drain terminals, as described below.In this embodiment, parallel switching functionality can be effectedbetween the first and second source/drain terminals of access FET 230 byindependently operating the particular ones of word lines WL0-WLm andcorresponding ones of word lines R0-Rm. For example, by independentlyactivating word line WL0 and word line R0, both of which are coupled tothe same row of memory cells 212, independently controlled inversionchannels can be formed in each corresponding access FET 230 byrespective first and second gates for allowing conduction between thefirst and second source/drain regions.

[0034] According to another aspect of the invention, each of the firstand second gates of access FET 230 is capable of controlling theconduction between its first and second source/drain terminals, but thefirst and second gates of particular access FETs 230 are synchronouslyactivated, rather than independently operated. For example, bysynchronously activating word line WL0 and word line R0, both of whichare coupled to the same row of memory cells 212, synchronously activatedinversion channels can be formed in each corresponding access FET 230 byrespective first and second gates for allowing conduction between thefirst and second source/drain regions.

[0035] In this embodiment, synchronous activation and deactivation ofthe first and second gates allows better control over the potentialdistributions in the access FET 230 when it is in a conductive state.Synchronous activation and deactivation can be used to obtainwell-controlled fully depleted operating characteristics of access FET230.

[0036] In a further embodiment in which the first and second gates areeither synchronously or independently activated, different activationvoltages can be applied to the first and second gates of the access FET230. For example, different voltages can be provided to synchronouslyactivated word lines WL0 and R0, thereby providing different activationvoltages to the first and second gates of the access FET 230 to obtainparticular desired operating characteristics. Similarly, differentdeactivation voltages can be applied to the first and second gates ofthe access FET 230. For example, different deactivation voltages can beprovided to synchronously deactivated word lines WL0 and R0 andcorresponding first and second gates of access FETs 230, in order toobtain particular desired operating characteristics. Similarly,different activation and deactivation voltages can be applied toindependently operated word lines such as WL0 and R0.

[0037]FIG. 3 is a diagram illustrating an access FET 300 formedaccording to the teachings of the present invention which make up aportion of the memory cells 212 shown in FIG. 2. As shown in FIG. 3,access FET 300 includes a vertical ultra thin body transistor, orotherwise stated an ultra thin single crystalline vertical transistor.According to the teachings of the present invention, the structure ofthe access FET 300 includes a pillar 301 extending outwardly from asemiconductor substrate 302. The pillar includes a single crystallinefirst contact layer 304 and a single crystalline second contact layer306 vertically separated by an oxide layer 308. An ultra thin singlecrystalline vertical transistor 310 is formed along side of the pillar301. The ultra thin single crystalline vertical transistor 310 includesan ultra thin single crystalline vertical body region 312 whichseparates an ultra thin single crystalline vertical first source/drainregion 314 and an ultra thin single crystalline vertical secondsource/drain region 316. A gate 318, which may be integrally formed witha word line as described above, is formed opposing the ultra thin singlecrystalline vertical body region 312 and is separated therefrom by athin gate oxide layer 320.

[0038] According to embodiments of the present invention, the ultra thinsingle crystalline vertical body region 312 includes a channel having avertical length (L) of less than 100 nanometers. Also, the ultra thinsingle crystalline vertical body region has a horizontal width (W) ofless than 10 nanometers. According to the teachings of the presentinvention, the ultra thin single crystalline vertical transistor 310 isformed from solid phase epitaxial growth.

[0039]FIG. 4A is a perspective view illustrating generally oneembodiment of a portion of an open bit line memory array 410 accordingto the present invention. FIG. 4 illustrates portions of six memorycells 401-1, 401-2, 401-3, 401-4, 401-5, and 401-6 which include ultrathin single crystalline vertical transistors 430. According to theteachings of the present invention, these ultra thin single crystallinevertical transistors 430 are formed, as described in connection withFIG. 3, along side of pillars extending outwardly from a semiconductorsubstrate 400. These pillars are formed on conductive segments of bitlines 402 which represent particular ones of bit lines BL0-BLn. In theembodiment shown in FIG. 4A conductive segments of first word line 406represents any one of word lines WL0-WLm, which provide integrallyformed first gates for ultra thin single crystalline verticaltransistors 430 on one side of a trench in which the particular firstword line 406 is interposed, depending on the desired circuitconfiguration as presented in connection with FIG. 2B. Conductivesegments of second word line 408 represents any one of word lines W0-Wm,which provide integrally formed second gates for ultra thin singlecrystalline vertical transistors 430 in a neighboring trench in whichthe particular second word line 408 is interposed.

[0040] As explained in connection with FIG. 3, ultra thin singlecrystalline vertical transistors 430 are formed alongside of pillarsthat extend outwardly from an underlying substrate 410. As describedbelow, substrate 400 includes bulk semiconductor starting material,semiconductor-on-insulator (SOI) starting material, or SOI material thatis formed from a bulk semiconductor starting material during processing.

[0041]FIG. 4A illustrates one example embodiment, using bulk siliconprocessing techniques. As shown in FIG. 4A, the pillars include an n+silicon layer formed on a bulk silicon substrate 400 to produce firstcontact layer 412 and integrally formed n++ conductively doped bit lines402 defining a particular column of memory cells shown as BL0-Bln inFIGS. 2A and 2B. An oxide layer 414 is formed on n+ first contact layer412. A further n+ silicon layer is formed on oxide layer 414 to producesecond contact layer 416 of in the pillars. Storage capacitors 432 areformed on the second contact layers 416 using any suitable technique asthe same will be known and understood by one of ordinary skill in theart upon reading this disclosure.

[0042] In the embodiment of FIG. 4A, word lines WL0-WLm are disposed(interdigitated) within the array 410. For example, first word line 406is interposed in a trench 431 between pillars of 401-1 and 401-3 andbetween pillars 401-2 and 401-4. Second word line 408 is interposed in atrench 432 between semiconductor pillars of memory cell pairs 401-3 and401-5 and between pillars 401-4 and 401-6. Thus, as seen from FIG. 4A,the ultra thin single crystalline vertical transistors 430 which areformed along side of the pillars are also in contact with bit lines 402through the first contact layers 412. In this embodiment, bit lines 402contact bulk semiconductor substrate 400.

[0043] Isolation trenches provide isolation between ultra thin singlecrystalline vertical transistors 430 of adjacent memory cells 401-1,401-2, 401-3, 401-4, 401-5, and 401-6. Columns of pillars along a bitline direction are separated by a trench 420 that is subsequently filledwith a suitable insulating material such as silicon dioxide. Forexample, a trench 420 provides isolation between pillars 401-1 and 401-2and between pillars 401-3 and 401-4. Rows of pillars including the ultrathin single crystalline vertical transistors 430 are altematinglyseparated by trenches 431 and 432, each of which contain word linesWL0-WLm as described above. Such word lines WL0-WLm are separated fromsubstrate 400 by an underlying insulating layer, described below, andseparated from the ultra thin vertically oriented single crystallinebody regions of ultra thin single crystalline vertical transistors 430(as described in connection with FIG. 3) by a gate oxide, also describedbelow. Trenches 431 and 432 extend substantially orthogonally to bitlines 402.

[0044] In one embodiment, respective first and second word lines 406 and408 are formed of a refractory metal, such as tungsten or titanium. Inanother embodiment, first and second word lines 406 and 408 can beformed of n+ doped polysilicon. Similarly, other suitable conductorscould also be used for first and second words lines 406 and 408,respectively. One of ordinary skill in the art will further understandupon reading this disclosure that the conductivity types describedherein can be reversed by altering doping types such that the presentinvention is equally applicable to include structures having ultra thinvertically oriented single crystalline p-channel type transistors 430.The invention is not so limited.

[0045] Burying first and second word lines 406 and 408 belowsemiconductor a top surface of the vertical pillars provides additionalspace on the upper portion of memory cells, 401-1, 401-2, 401-3, 401-4,401-5, and 401-6, for formation of storage capacitors 432. Increasingthe area available for forming storage capacitor 432 increases thepossible obtainable capacitance value of storage capacitor 432. In oneembodiment, storage capacitor 432 is a stacked capacitor that is formedusing any of the many capacitor structures and process sequences knownin the art. Other techniques could also be used for implementing storagecapacitor 432. Contacts to the first and second word lines 406 and 408,respectively, can be made outside of the memory array 410.

[0046]FIG. 4B is a top view of FIG. 4A illustrating generally pillarsincluding the ultra thin single crystalline vertical transistors 430.FIG. 4B illustrates subsequently formed insulator such as oxide 424,formed in trenches 420 to provide isolation between the pillarsincluding the ultra thin single crystalline vertical transistors 430. Inthis embodiment, first word line 406 is between adjacent pillarsincluding the ultra thin single crystalline vertical transistors 430 ina given column, such as between pillars 401-1 and 401-3 which arecoupled to the same bit line. First word line 406 is shared betweenadjacent pillars including the ultra thin single crystalline verticaltransistors 430 that are in a given row, e.g. 401-1 and 401-2, butcoupled to different bit lines 402. First word line 406 is located intrench 431 that extends between the pillars 401-1 and 401-3. First wordline 406 is separated by gate oxide 418 from the vertically orientedsingle crystalline ultra thin body regions in the ultra thin singlecrystalline vertical transistors 430 alongside of the pillars on theside of trench 431.

[0047] Second word line 408 is shared between adjacent pillars includingthe ultra thin single crystalline vertical transistors 430 in a givenrow, such as between pillars 401-1 and 401-2, but coupled to differentbit lines 402. Second word line 408 is also between adjacent pillarsincluding the ultra thin single crystalline vertical transistors 430that are in the same column, such as between pillars 401-1 and 401-3 andcoupled to the same bit line 402. The structural relationship for secondword line 408 is thus analogous to that for first word line 406.

[0048] As illustrated in the plan view of FIG. 4B, respective first andsecond word lines 406 and 408 are shared between pillars including theultra thin single crystalline vertical transistors 430. As a result,only one surface line width of each is allocated to each memory cell.The row pitch of each cell, measured from the centerline of first wordline 406 to the centerline of second word line 408, can be approximately3F, where F is a minimum lithographic feature size. F corresponds to thelength and width presented by the surface of a minimum-sizedsemiconductor pillar in each memory cell, 401-1, 401-2, 401-3, 401-4,401-5, and 401-6. The column pitch of each cell, measured betweencenterlines of bit lines 402 can be approximately b 2 F. Thus, thesurface area of each memory cell, 401-1, 401-2, 401-3, 401-4, 401-5, and401-6, can be approximately 6 F².

[0049]FIG. 4C is a perspective view illustrating another embodiment of aportion of an open bit line memory array 410 according to the presentinvention. FIG. 4C illustrates portions of six memory cells 401-1,401-2, 401-3, 401-4, 401-5, and 401-6 which include ultra thin singlecrystalline vertical transistors 430. According to the teachings of thepresent invention, these ultra thin single crystalline verticaltransistors 430 are formed, as described in connection with FIG. 3,along side of pillars extendingly outwardly from a semiconductorsubstrate 400. These pillars are formed on conductive segments of bitlines 402 which represent particular ones of bit lines BL0-BLn. In theembodiment shown in FIG. 4C conductive segments of first word line 406Aand 406B represent any one of word lines WL0-WLm, which provideintegrally formed first gates for ultra thin single crystalline verticaltransistors 430 on opposing sides of a trench in which the particularfirst word lines 406A and 406B are interposed, depending on the desiredcircuit configuration as presented in connection with FIGS. 2A and 2B.Conductive segments of second word line 408A and 408B represent any oneof word lines R0-RM, which provide integrally formed second gates forultra thin single crystalline vertical transistors 430 on opposing sidesof a trench in which the particular second word lines 408A and 408B areinterposed. Thus, word lines WL0-WLm and R0-Rm are alternatinglydisposed (interdigitated) within the array 410.

[0050] As explained in connection with FIG. 3, ultra thin singlecrystalline vertical transistors 430 are formed alongside of pillarsthat extend outwardly from an underlying substrate 410. As describedbelow, substrate 400 includes bulk semiconductor starting material,semiconductor-on-insulator (SOI) starting material, or SOI material thatis formed from a bulk semiconductor starting material during processing.

[0051]FIG. 4C illustrates one example embodiment, using bulk siliconprocessing techniques. As shown in FIG. 4C, the pillars include ann+silicon layer formed on a bulk silicon substrate 400 to produce firstcontact layer 412 and integrally formed n++ conductively doped bit lines402 defining a particular column of memory cells shown as BL0-Bln inFIGS. 2A and 2B. An oxide layer 414 is formed on n+ first contact layer412. A further n+ silicon layer is formed on oxide layer 414 to producesecond contact layer 416 of in the pillars. Storage capacitors 432 areformed on the second contact layers 416 using any suitable technique asthe same will be known and understood by one of ordinary skill in theart upon reading this disclosure.

[0052] Word lines WL0-WLm and R0-RM are alternatingly disposed(interdigitated) within the array 410. For example, first word lines406A and 406B are interposed in a trench 431 between pillars of 401-1and 401-3 and between pillars 401-2 and 401-4 and separated by aninsulator material such as an oxide. Second word lines 408A and 408B areinterposed in a trench 432 between semiconductor pillars of memory cellpairs 401-3 and 401-5 and between pillars 401-4 and 401-6 and separatedby an insulator material such as an oxide. As shown in the embodiment ofFIG. 4C, the first and second wordlines 406A, 406B and 408A, 408Brespectively, are integrally formed as gates for the ultra thin singlecrystalline vertical transistors 430 which are formed along side of thepillars such that the wordlines couple with the ultra thin singlecrystalline vertical transistors 430 in each row adjacent pillar to formthe open bit line DRAM device of the present invention. Also, as seenfrom FIG. 4C, the ultra thin single crystalline vertical transistors 430which are formed along side of the pillars are in contact with bit lines402 through the first contact layers 412. In this embodiment, bit lines402 contact bulk semiconductor substrate 400.

[0053] Isolation trenches provide isolation between ultra thin singlecrystalline vertical transistors 430 of adjacent memory cells 401-1,401-2, 401-3, 401-4, 401-5, and 401-6. Columns of pillars along a bitline direction are separated by a trench 420 that is subsequently filledwith a suitable insulating material such as silicon dioxide. Forexample, a trench 420 provides isolation between pillars 401-1 and 401-2and between pillars 401-3 and 401-4. Rows of pillars including the ultrathin single crystalline vertical transistors 430 are altematinglyseparated by trenches 431 and 432, each of which contain word linesWL0-WLm and R0-Rm as described above. Such word lines WL0-WLm and R0-Rmare separated from substrate 400 by an underlying insulating layer,described below, and separated from the ultra thin vertically orientedsingle crystalline body regions of ultra thin single crystallinevertical transistors 430 (as described in connection with FIG. 3) by agate oxide, also described below. Trenches 431 and 432 extendsubstantially orthogonally to bit lines 402.

[0054] In one embodiment, respective first and second word lines, 406A,406B and 408A, 408B respectively, are formed of a refractory metal, suchas tungsten or titanium. In another embodiment, first and second wordlines 406 and 408 can be formed of n+doped polysilicon. Similarly, othersuitable conductors could also be used for first and second word lines,406A, 406B and 408A, 408B respectively. One of ordinary skill in the artwill further understand upon reading this disclosure that theconductivity types described herein can be reversed by altering dopingtypes such that the present invention is equally applicable to includestructures having ultra thin vertically oriented single crystallinep-channel type transistors 430. The invention is not so limited.

[0055] Burying first and second word lines, 406A, 406B and 408A, 408Brespectively, below semiconductor a top surface of the vertical pillarsprovides additional space on the upper portion of memory cells, 401-1,401-2, 401-3, 401-4, 401-5, and 401-6, for formation of storagecapacitors 433. Increasing the area available for forming storagecapacitor 433 increases the possible obtainable capacitance value ofstorage capacitor 433. In one embodiment, storage capacitor 433 is astacked capacitor that is formed using any of the many capacitorstructures and process sequences known in the art. Other techniquescould also be used for implementing storage capacitor 433. Contacts tothe first and second word lines, 406A, 406B and 408A, 408B respectively,can be made outside of the memory array 410.

[0056]FIG. 4D is a cross sectional view taken along cut-line 4D-4D ofFIG. 4C illustrating generally pillars including the ultra thin singlecrystalline vertical transistors 430. As shown in FIG. 4D, first wordlines 406A and 406B are formed on opposing sides of trench 431 adjacentpillars including the ultra thin single crystalline vertical transistors430 in a given column, such as between pillars 401-2 and 401-4 which arecoupled to the same bit line. As was shown in FIG. 4C, first word lines406A and 406B are also shared between adjacent pillars including theultra thin single crystalline vertical transistors 430 that are in theadjacent columns, but coupled to different bit lines 402 and thus formthe open bit line DRAM device. First word lines 406A and 406B areseparated by gate oxides 418 from the vertically oriented singlecrystalline ultra thin body regions in the ultra thin single crystallinevertical transistors 430 alongside of the pillars on each side of trench431.

[0057] As shown in FIG. 4D, second word lines 408A and 408B are formedon opposing sides of trench 432 adjacent pillars including the ultrathin single crystalline vertical transistors 430 in a given column, suchas between pillars 401-4 and 401-6 which are coupled to the same bitline. As was shown in FIG. 4C, second word lines 408A and 408B are alsoshared between adjacent pillars including the ultra thin singlecrystalline vertical transistors 430 that are in the adjacent columns,but coupled to different bit lines 402 and thus form the open bit lineDRAM device. Second word lines 408A and 408B are separated by gateoxides 418 from the vertically oriented single crystalline ultra thinbody regions in the ultra thin single crystalline vertical transistors430 alongside of the pillars on each side of trench 432. The structuralrelationship for second word lines 408A and 408B are analogous to thatfor first word lines 406A and 406B.

[0058] FIGS. 5A-5C illustrate an initial process sequence for formingpillars along side of which vertical ultra thin body transistors canlater be formed as part of forming an open bit line DRAM according tothe teachings of the present invention. The dimensions suggested areappropriate to a 0.1 μm cell dimension (CD) technology and may be scaledaccordingly for other CD sizes. In the embodiment of FIG. 5A, a p-typebulk silicon substrate 510 starting material is used. An n++ and n+silicon composite first contact layer 512 is formed on substrate 510,such as by ion-implantation, epitaxial growth, or a combination of suchtechniques to form a single crystalline first contact layer 512.According to the teachings of the present invention, the more heavilyconductively doped lower portion of the first contact layer 512 alsofunctions as the bit line 502. The thickness of the n++ portion of firstcontact layer 512 is that of the desired bit line 502 thickness, whichcan be approximately between 0.1 to 0.25 μm. The overall thickness ofthe first contact layer 512 can be approximately between 0.2 to 0.5 μm.An oxide layer 514 of approximately 100 nanometers (nm), 0.1 μm,thickness or less is formed on the first contact layer 512. In oneembodiment, the oxide layer 514 can be formed by thermal oxide growthtechniques. A second contact layer 516 of n+ silicon is formed on theoxide layer 514 to form a polycrystalline second contact layer 516. Thesecond contact layer 516 is formed to a thickness of 100 nm or less.

[0059] Next, a thin silicon dioxide layer (SiO₂) 518 of approximately 10nm is deposited on the second contact layer 516. A thicker siliconnitride layer (Si₃N₄) 520 of approximately 20 to 50 nm in thickness isdeposited on the thin silicon dioxide layer (SiO₂) 518 to form padlayers, e.g. layers 518 and 520. These pad layers 518 and 520 can bedeposited using any suitable technique such as by chemical vapordeposition (CVD).

[0060] A photoresist is applied and selectively exposed to provide amask for the directional etching of trenches 525, such as by reactiveion etching (RIE). The directional etching results in a plurality ofcolumn bars 530 containing the stack of nitride layer 520, pad oxidelayer 518, second contact layer 516, oxide layer 514, and first contactlayer 512. Trenches 525 are etched to a depth that is sufficient toreach the surface 532 of substrate 510, thereby providing separationbetween conductively doped bit lines 502. The photoresist is removed.Bars 530 are now oriented in the direction of bit lines 502. In oneembodiment, bars 530 have a surface line width of approximately 0.1micron or less. The width of each trench 525 can be approximately equalto the line width of bars 530. The structure is now as appears in FIG.5A.

[0061] In FIG. 5B, isolation material 532, such as SiO₂ is deposited tofill the trenches 525. The working surface is then planarized, such asby chemical mechanical polishing/planarization (CMP). A secondphotoresist is applied and selectively exposed to provide a mask for thedirectional etching of trenches 535 orthogonal to the bit line 502direction. Trenches 535 can be formed using any suitable technique suchas by reactive ion etching (RIE). Trenches 535 are etched through theexposed SiO₂ and the exposed stack of nitride layer 520, pad oxide layer518, second contact layer 516, oxide layer 514, and into the firstcontact layer 512 but only to a depth sufficient to leave the desiredbit line 502 thickness, e.g. a remaining bit line thickness of typically100 nm. The structure is now as appears in FIG. 5B having individuallydefined pillars 540-1, 540-2, 540-3, and 540-4.

[0062]FIG. 5C illustrates a cross sectional view of the structure shownin FIG. 5B taken along cut-line 5C-5C. FIG. 5C shows the continuous bitline 502 connecting adjacent pillars 540-1 and 540-2 in any givencolunm. Trench 535 remains for the subsequent formation of wordlines, asdescribed below, in between adjacent rows of the pillars, such as a rowformed by pillars 540-1 and 540-4 and a row formed by pillars 540-2, and540-3.

[0063] FIGS. 6A-6C illustrate that the above techniques described inconnection with FIGS. 5A-5C can be implemented on a bulk CMOS technologysubstrate or a silicon on insulator (SOI) technology substrate. FIG. 6Arepresents the completed sequence of process steps shown in FIGS. 5A-5C,minus the pad layers, formed on a lightly doped p-type bulk siliconsubstrate 610. The structure shown in FIG. 6A is similar to the crosssectional view in FIG. 5C and shows a continuous bit line 602 withpillar stacks 640-1 and 640-2 formed thereon. The pillars 640-1 and640-2 include an n+ first contact layer 612, an oxide layer 614 formedthereon, and a second n+ contact layer 616 formed on the oxide layer614.

[0064]FIG. 6B represents the completed sequence of process steps shownin FIGS. 5A-5C, minus the pad layers, formed on a commercial SOI wafer,such as SIMOX. As shown in FIG. 6B, a buried oxide layer 611 is presenton the surface of the substrate 610. The structure shown in FIG. 6B isalso similar to the cross sectional view in FIG. 5C and shows acontinuous bit line 602 with pillar stacks 640-1 and 640-2 formedthereon, only here the continuous bit line 602 is separated from thesubstrate 610 by the buried oxide layer 611. Again, the pillars 640-1and 640-2 include an n+ first contact layer 612, an oxide layer 614formed thereon, and a second n+ contact layer 616 formed on the oxidelayer 614.

[0065]FIG. 6C represents the completed sequence of process steps shownin FIGS. 5A-5C, minus the pad layers, forming islands of silicon on aninsulator, where the insulator 613 has been formed by oxide under cuts.Such a process includes the process described in more detail in U.S.Pat. No. 5,691,230, by Leonard Forbes, entitled “Technique for ProducingSmall Islands of Silicon on Insulator,” issued Nov. 25, 1997, which isincorporated herein by reference. The structure shown in FIG. 6C is alsosimilar to the cross sectional view in FIG. 5C and shows a continuousbit line 602 with pillar stacks 640-1 and 640-2 formed thereon, onlyhere the continuous bit line 602 is separated from the substrate 610 bythe insulator 613 which has been gformed nby oxide under cuts such asaccording to the process referenced above. Again, the pillars 640-1 and640-2 include an n+ first contact layer 612, an oxide layer 614 formedthereon, and a second n+ contact layer 616 formed on the oxide layer614. Thus, according t6o the teachings of the present invention, thesequence of process steps to form pillars, as shown in FIGS. 5A-5C, caninclude forming the same on at least three different types of substratesas shown in FIGS. 6A-6C.

[0066] FIGS. 7A-7C illustrate a process sequence continuing from thepillar formation embodiments provided in FIGS. 5A-5C, and any of thesubstrates shown in FIGS. 6A-76C, to form vertical ultra thin bodytransistors along side of the pillars, such as pillars 5401-1 and 540-2in FIG. 5C. For purposes of illustration only, FIG. 7A illustrates anembodiment pillars 740-1 and 740-2 formed on a p-type substrate 710 andseparated by a trench 730. Analogous to the description provided inconnection FIGS. 5A-5C, FIG. 7A shows a first single crystalline n+contact layer 712 a portion of which, in one embodiment, is integrallyformed with an n++ bit line 702. An oxide layer region 714 is formed inpillars 740-1 and 740-2 on the first contact layer 712. A second n+contact layer 716 is shown formed on the oxide layer region 714 in thepillars 740-1 and 740-2. And, pad layers of (SiO₂) 718 and (Si₃N₄) 720,respectively are shown formed on the second contact layer 716 in thepillars 740-1 and 740-2.

[0067] In FIG. 7B, a lightly doped p-type polysilicon layer 745 isdeposited over the pillars 740-1 and 740-2 and directionally etched toleave the lightly doped p-type material 745 on the sidewalls 750 of thepillars 740-1 and 740-2. In one embodiment according to the teachings ofthe present invention, the lightly doped p-type polysilicon layer isdirectionally etched to leave the lightly doped p-type material 745 onthe sidewalls 750 of the pillars 740-1 and 740-2 having a width (W), orhorizontal thickness of 10 nm or less. The structure is now as shown inFIG. 7B.

[0068] The next sequence of process steps is described in connectionwith FIG. 7C. At this point another masking step, as the same has beendescribed above, can be employed to isotropically etch the polysilicon745 off of some of the sidewalls 750 and leave polysilicon 745 only onone sidewall of the pillars 740-1 and 740-2 if this is required by someparticular configuration, e.g. forming ultra thin body transistors onlyon one side of pillars 740-1 and 740-2.

[0069] In FIG. 7C, the embodiment for forming the ultra thin singlecrystalline vertical transistors, or ultra thin body transistors, onlyon one side of pillars 740-1 and 740-2 is shown. In FIG. 7C, the waferis heated at approximately 550 to 700 degrees Celsius. In this step, thepolysilicon 745 will recrystallize and lateral epitaxial solid phaseregrowth will occur vertically. As shown in FIG. 7C, the singlecrystalline silicon at the bottom of the pillars 740-1 and 740-2 willseed this crystal growth and an ultrathin single crystalline film 746will form which can be used as the channel of an ultra thin singlecrystalline vertical MOSFET transistor. In the embodiment of FIG. 7C,where the film is left only on one side of the pillar, thecrystallization will proceed vertically and into the n+ polysiliconsecond contact material/layer 716 on top of the pillars 740-1 and 740-2.If however, both sides of the pillars 740-1 and 740-2 are covered, thecrystallization will leave a grain boundary near the center on top ofthe pillars 740-1 and 740-2. This embodiment is shown in FIG. 7D.

[0070] As shown in FIGS. 7C and 7D, drain and source regions, 751 and752 respectively, will be formed in the ultrathin single crystallinefilm 746 along the sidewalls 750 of the pillars 740-1 and 740-2 in theannealing process by an out diffusion of the n+ doping in the first andthe second contact layers, 712 and 716. In the annealing process, theseportions of the ultrathin single crystalline film 746, now with the n+dopant, will similarly recrystallize into single crystalline structureas the lateral epitaxial solid phase regrowth occurs vertically. Thestructure is now as shown in FIGS. 7C or 7D. As one of ordinary skill inthe art will understand upon reading this disclosure. A conventionalgate insulator can be grown or deposited on this ultrathin singlecrystalline film 746. And, either horizontal or vertical gate structurescan be formed in trenches 730.

[0071] As one of ordinary skill in the art will understand upon readingthis disclosure, drain and source regions, 751 and 752 respectively,have been formed in an ultrathin single crystalline film 746 to form aportion of the ultra thin single crystalline vertical transistors, orultra thin body transistors, according to the teachings of the presentinvention. The ultrathin single crystalline film 746 now includes anultra thin single crystalline vertical first source/drain region 751coupled to the first contact layer 712 and an ultra thin singlecrystalline vertical second source/drain region 752 coupled to thesecond contact layer 716. An ultra thin p-type single crystallinevertical body region 753 remains along side of, or opposite, the oxidelayer 714 and couples the first source/drain region 751 to the secondsource/drain region 752. In effect, the ultra thin p-type singlecrystalline vertical body region 753 separates the drain and sourceregions, 751 and 752 respectively, and can electrically couple the drainand source regions, 751 and 752, when a channel is formed therein by anapplied potential. The drain and source regions, 751 and 752respectively, and the ultra thin body region 753 are formed of singlecrystalline material by the lateral solid phase epitaxial regrowth whichoccurs in the annealing step.

[0072] The dimensions of the structure now include an ultra thin singlecrystalline body region 753 having a vertical length of less than 100 nmin which a channel having a vertical length of less than 100 nm can beformed. Also, the dimensions include drain and source regions, 751 and752 respectively, having a junction depth defined by the horizontalthickness of the ultrathin single crystalline film 746, e.g. less than10 nm. Thus, the invention has provided junction depths which are muchless than the channel length of the device and which are scalable asdesign rules further shrink. Further, the invention has provided astructure for transistors with ultra thin bodies so that a surface spacecharge region in the body of the transistor scales down as othertransistor dimensions scale down. In effect, the surface space chargeregion has been minimized by physically making the body region of theMOSFET ultra thin, e.g. 10 nm or less.

[0073] One of ordinary skill in the art will further understand uponreading this disclosure that the conductivity types described herein canbe reversed by altering doping types such that the present invention isequally applicable to include structures having ultra thin verticallyoriented single crystalline p-channel type transistors 430. Theinvention is not so limited. From the process descriptions describedabove, the fabrication process can continue to form a number ofdifferent horizontal and vertical gate structure embodiments in thetrenches 730 as described in connection with the Figures below.

[0074] FIGS. 8A-8C illustrate a process sequence for forming ahorizontal gate structure embodiment, referred to herein as horizontalreplacement gates, in connection with the present invention. Thedimensions suggested in the following process steps are appropriate to a0.1 micrometer CD technology and may be scaled accordingly for other CDsizes. FIG. 8A represents a structure similar to that shown in FIG. 7C.That is FIG. 8A shows an ultrathin single crystalline film 846 along thesidewalls 850 of pillars 840-1 and 840-2 in trenches 830. The ultrathinsingle crystalline film 846 at this point includes an ultra thin singlecrystalline vertical first source/drain region 851 coupled to a firstcontact layer 812 and an ultra thin single crystalline vertical secondsource/drain region 852 coupled to a second contact layer 816. An ultrathin p-type single crystalline vertical body region 853 is present alongside of, or opposite, an oxide layer 814 and couples the firstsource/drain region 851 to the second source/drain region 852. Accordingto the process embodiment shown in FIG. 8A an n+ doped oxide layer 821,or PSG layer as the same will be known and understood by one of ordinaryskill in the art will understand, is deposited over the pillars 840-1and 840-2 such as by a CVD technique. This n+ doped oxide layer 821 isthen planarized to remove off of the top surface of the pillars 840-1and 840-2. An etch process is performed to leave about 50 nm at thebottom of trench 830. Next, an undoped polysilicon layer 822 or undopedoxide layer 822 is deposited over the pillars 840-1 and 840-2 and CMPplanarized to again remove from the top surface of the pillars 840-1 and840-2. Then, the undoped polysilicon layer 822 is etched, such as by RIEto leave a thickness of 100 nm or less in the trench 830. Next, anothern+ doped oxide layer 823, or PSG layer as the same will be known andunderstood by one of ordinary skill in the art will understand, isdeposited over the pillars 840-1 and 840-2 such as by a CVD process. Thestructure is now as appears in FIG. 8A.

[0075]FIG. 8B illustrates the structure following the next sequence offabrication steps. In FIG. 8B, a heat treatment is applied to diffusethe n-type dopant out of the PSG layers, e.g. 821 and 823 respectively,into the vertical ultrathin single crystalline film 846 to additionallyform the drain and source regions, 851 and 852 respectively. Next, asshown in FIG. 8B, a selective etch is performed, as the same will beknown and understood by one of ordinary skill in the art upon readingthis disclosure, to remove the top PSG layer 823 and the undopedpolysilicon layer 822, or oxide layer 822 in the trench 830. Thestructure is now as appears in FIG. 8B.

[0076] Next, in FIG. 8C, a thin gate oxide 825 is grown as the same willbe known and understood by one of ordinary skill in the art, such as bythermal oxidation, for the ultra thin single crystalline verticaltransistors, or ultra thin body transistors on the surface of the ultrathin single crystalline vertical body region 853. Next, doped n+ typepolysilicon layer 842 can be deposited to form a gate 842 for the ultrathin single crystalline vertical transistors, or ultra thin bodytransistors. The structure then undergoes a CMP process to remove thedoped n+ type polysilicon layer 842 from the top surface of the pillars840-1 and 840-2 and RIE etched to form the desired thickness of the gate842 for the ultra thin single crystalline vertical transistors, or ultrathin body transistors. In one embodiment, the doped n+ type polysiliconlayer 842 is RIE etched to form an integrally formed, horizontallyoriented word line/gate having a vertical side of less than 100nanometers opposing the ultra thin single crystalline vertical bodyregion 853. Next, an oxide layer 844 is deposited such as by a CVDprocess and planarized by a CMP process to fill trenches 830. An etchprocess is performed, as according to the techniques described above tostrip the nitride layer 820 from the structure. This can include aphosphoric etch process using phosphoric acid. The structure is now asappears as is shown in FIG. 8C.

[0077] As one of ordinary skill in the art will understand upon readingthis disclosure, contacts can be formed to the second contact layer 816on top of the pillars 840-1 and 840-2 to continue with capacitorformation and standard BEOL processes.

[0078] FIGS. 9A-9C illustrate a process sequence for forming a verticalgate structure embodiment according to the teachings of the presentinvention. The dimensions suggested in the following process steps areappropriate to a 0.1 micrometer CD technology and may be scaledaccordingly for other CD sizes. FIG. 9A represents a structure similarto that shown in FIG. 7C. That is FIG. 9A shows an ultrathin singlecrystalline film 956 along the sidewalls 950 of pillars 940-1 and 940-2in trenches 930. The ultrathin single crystalline film 956 at this pointincludes an ultra thin single crystalline vertical first source/drainregion 951 coupled to a first contact layer 912 and an ultra thin singlecrystalline vertical second source/drain region 952 coupled to a secondcontact layer 916. An ultra thin p-type single crystalline vertical bodyregion 953 is present along side of, or opposite, an oxide layer 914 andcouples the first source/drain region 951 to the second source/drainregion 952. According to the process embodiment shown in FIG. 9A aconformal nitride layer of approximately 20 nm is deposited, such as byCVD, and directionally etched to leave only on the sidewalls 950. Aoxide layer 921 is then grown, such as by thermal oxidation, to athickness of approximately 50 nm in order to insulate the exposed bitline bars 902. The nitride layer is then stripped, using conventionalstripping processes as the same will be known and understood by one ofordinary skill in the art. The structure is now as appears in FIG. 9A.

[0079] As shown in FIG. 9B, a thin gate oxide layer 957 is grown on thesidewalls 950 of the ultrathin single crystalline film 956 for the ultrathin single crystalline vertical transistors, or ultra thin bodytransistors.

[0080] In FIG. 9C, a wordline conductor of an n+ doped polysiliconmaterial or suitable metal 941 is deposited to a thickness ofapproximately 50 nm or less. This wordline conductor 941 is thendirectionally etched to leave only on the vertical thin gate oxidelayers 957 on the pillars forming separate vertical, integrally formedwordline/gates 941A and 941B. The structure is now as appears in FIG.9C.

[0081] In FIG. 9D, an oxide layer 954 is deposited, such as by CVD, inorder to fill the spaces in the trenches 930 between the separatevertical, integrally formed wordline/gates 941A and 941B of neighboringpillars 940-1 and 940-2. The oxide layer 954 is planarized by CMP toremove from the top of the pillars 940-1 and 940-2. Then the remainingpad material 918 and 920 is etched, such as by RIE, to remove from thetop of the pillars 940-1 and 940-2. Next, deposit CVD oxide 955 to coverthe surface of the pillars 940-1 and 940-2. The structure is now asappears in FIG. 9D. As one of ordinary skill in the art will understandupon reading this disclosure, the process can now proceed with storagecapacitor formation and BEOL process steps.

[0082] As one of ordinary skill in the art will understand upon readingthis disclosure, the process steps described above produce integrallyformed vertically oriented wordline conductors/gates 941A and 941B whichserve as vertical gates along the sides of the pillars 940-1 and 940-2.This produces an open bit line DRAM structure embodiment which issimilar the perspective view of FIG. 4C and the cross sectional viewtaken along the direction of the bit lines in FIG. 4D.

CONCLUSION

[0083] The above structures and fabrication methods have been described,by way of example, and not by way of limitation, with respect to an openbit line DRAM with ultra thin body transistors. Different types of gatestructures are shown which can be utilized on three different types ofsubstrates to form open bit line DRAM memory arrays.

[0084] It has been shown that higher and higher density requirements inDRAMs result in smaller and smaller dimensions of the structures andtransistors. Conventional planar transistor structures are difficult toscale to the deep sub-micron dimensional regime. The present inventionprovides vertical access or transfer transistor devices which arefabricated in ultra-thin single crystalline silicon films grown alongthe sidewall of an oxide pillar. These transistors with ultra-thin bodyregions scale naturally to smaller and smaller dimensions whilepreserving the performance advantage of smaller devices. The advantagesof smaller dimensions for higher density and higher performance are bothachieved in open bit line memory arrays.

What is claimed is:
 1. A transistor, comprising: a pillar extendingoutwardly from a semiconductor substrate, wherein the pillar includes asingle crystalline first contact layer and a single crystalline secondcontact layer vertically separated by an oxide layer; a singlecrystalline vertical transistor is formed along side of the pillar,wherein the single crystalline vertical transistor includes an ultrathin single crystalline vertical body region which separates an ultrathin single crystalline vertical first source/drain region and an ultrathin single crystalline vertical second source/drain region; and a gateopposing the ultra thin single crystalline vertical body region. 2 . Thetransistor of claim 1, wherein the ultra thin single crystallinevertical body region includes a channel having a vertical length of lessthan 100 nanometers. 3 . The transistor of claim 1, wherein the ultrathin single crystalline vertical body region has a horizontal width ofless than 10 nanometers.
 4. The transistor of claim 1, wherein the ultrathin single crystalline vertical body region is formed from solid phaseepitaxial growth.
 5. A memory cell, comprising: a pillar extendingoutwardly from a semiconductor substrate, wherein the pillar includes asingle crystalline first contact layer and a single crystalline secondcontact layer separated by an oxide layer; a single crystalline verticaltransistor formed along side of the pillar, wherein the singlecrystalline vertical transistor includes; an ultra thin singlecrystalline vertical first source/drain region coupled to the firstcontact layer; an ultra thin single crystalline vertical secondsource/drain region coupled to the second contact layer; an ultra thinsingle crystalline vertical body region formed along side of the oxidelayer, wherein the single crystalline vertical body region couples thefirst source/drain region to the second source/drain region; and a gateopposing the vertical body region and separated therefrom by a gateoxide; a buried bit line formed of single crystalline semiconductormaterial and disposed below the ultra thin single crystalline verticalbody region, wherein the buried bit line is coupled to the first contactlayer; a capacitor coupled to the second contact layer; and a word linedisposed orthogonally to the buried bit line in a trench below a topsurface of the pillar for addressing the gate.
 6. The memory cell ofclaim 5, wherein the buried bit line is more heavily doped than thefirst contact layer and is formed integrally with the first contactlayer.
 7. The memory cell of claim 5, wherein the ultra thin singlecrystalline vertical body region includes a p-type channel having avertical length of less than 100 nanometers.
 8. The memory cell of claim7, wherein the ultra thin single crystalline vertical body region has ahorizontal width of less than 10 nanometers.
 9. The memory cell of claim5, wherein the pillar extends outwardly from an insulating portion ofthe semiconductor substrate.
 10. The memory cell of claim 5, wherein thesemiconductor substrate includes a silicon on insulator substrate. 11.The memory cell of claim 5, wherein the gate includes a horizontallyoriented gate, wherein a vertical side of the horizontally oriented gatehas a length of less than 100 nanometers.
 12. The memory cell of claim5, wherein the gate includes a vertically oriented gate having avertical length of less than 100 nanometers.
 13. A memory cell,comprising: a pillar extending outwardly from a semiconductor substrate,wherein the pillar includes a single crystalline first contact layer anda single crystalline second contact layer separated by an oxide layer; apair of single crystalline vertical transistors formed along opposingsides of the pillar, wherein each single crystalline vertical transistorincludes; an ultra thin single crystalline vertical first source/drainregion coupled to the first contact layer; an ultra thin singlecrystalline vertical second source/drain region coupled to the secondcontact layer; an ultra thin single crystalline vertical body regionformed along side of the oxide layer, wherein the single crystallinevertical body region couples the first source/drain region to the secondsource/drain region; and a gate opposing the vertical body region andseparated therefrom by a gate oxide; a buried bit line formed of singlecrystalline semiconductor material and disposed below the singlecrystalline vertical body regions, wherein the buried bit line iscoupled to the first contact layer; a capacitor coupled to the secondcontact layer; and a pair of wordlines, wherein each wordlineindependently addresses one of the gates for the pair of singlecrystalline vertical transistors.
 14. The memory cell of claim 13,wherein each of the pair of wordlines is independently disposed in apair of trenches on opposing sides of the pillar such that the pair ofwordlines are orthogonal to the buried bit line and below a top surfaceof the pillar.
 15. The memory cell of claim 13, wherein each ultra thinsingle crystalline vertical body region includes a p-type channel havinga vertical length of less than 100 nanometers.
 16. The memory cell ofclaim 13, wherein the buried bit line is formed integrally with thefirst contact layer and is separated from the semiconductor substrate byan oxide layer.
 17. The memory cell of claim 13, wherein each gateincludes a horizontally oriented gate having a vertical side length ofless than 100 nanometers.
 18. The memory cell of claim 13, wherein eachgate includes a vertically oriented gate having a vertical length ofless than 100 nanometers.
 19. An open bit line DRAM device, comprising:an array of memory cells, wherein each memory cell in the array ofmemory cells includes: a pillar extending outwardly from a semiconductorsubstrate, wherein the pillar includes a single crystalline firstcontact layer and a single crystalline second contact layer separated byan oxide layer; a single crystalline vertical transistor formed alongside of the pillar, wherein the single crystalline vertical transistorincludes; an ultra thin single crystalline vertical first source/drainregion coupled to the first contact layer; an ultra thin singlecrystalline vertical second source/drain region coupled to the secondcontact layer; an ultra thin single crystalline vertical body regionwhich opposes the oxide layer and couples the first and the secondsource/drain regions; and a gate opposing the vertical body region andseparated therefrom by a gate oxide; a plurality of buried bit linesformed of single crystalline semiconductor material and disposed belowthe pillars in the array memory cells for interconnecting with the firstcontact layer of column adjacent pillars in the array of memory cells;and a plurality of word lines, each word line disposed orthogonally tothe plurality of buried bit lines in a trench between rows of thepillars for addressing gates of the single crystalline verticaltransistors that are adjacent to the trench.
 20. The open bit line DRAMdevice of claim 19, wherein each single crystalline vertical body regionincludes a p-type channel having a vertical length of less than 100nanometers.
 21. The open bit line DRAM device of claim 19, wherein eachof the plurality of buried bit lines is separated by an oxide layer fromthe semiconductor substrate.
 22. The open bit line DRAM device of claim19, wherein each gate along a row of pillars is integrally formed withone of the plurality of word lines in the adjacent trench, and whereineach of the plurality of word lines includes a horizontally orientedword line having a vertical side of less than 100 nanometers opposingthe single crystalline vertical body regions.
 23. The open bit line DRAMdevice of claim 19, wherein each gate along a row of pillars isintegrally formed with one of the plurality of word lines in theadjacent trench, and wherein each of the plurality of word linesincludes a vertically oriented word line having a vertical length ofless than 100 nanometers.
 24. A memory device, comprising: an array ofmemory cells, wherein each memory cell in the array of memory cellsincludes: a pillar extending outwardly from a semiconductor substrate,wherein the pillar includes a single crystalline first contact layer anda single crystalline second contact layer separated by an oxide layer; apair of single crystalline vertical transistors formed along opposingsides of each pillar, wherein each single crystalline verticaltransistor includes; an ultra thin single crystalline vertical firstsource/drain region coupled to the first contact layer; an ultra thinsingle crystalline vertical second source/drain region coupled to thesecond contact layer; an ultra thin single crystalline vertical bodyregion formed along side of the oxide layer and which couples the firstand the second source/drain regions; and a gate opposing the verticalbody region and separated therefrom by a gate oxide; a plurality ofburied bit lines formed of single crystalline semiconductor material anddisposed below the pillars in the array memory cells for interconnectingwith the first contact layer of column adjacent pillars in the array ofmemory cells; and a plurality of word lines, each word line disposedorthogonally to the plurality of buried bit lines in a trench betweenrows of the pillars for addressing gates of the single crystallinevertical transistors that are adjacent to the trench, and wherein eachgate along a row of pillars is integrally formed with the word line inthe adjacent trench.
 25. The memory device of claim 24, wherein eachword line addresses gates for the single crystalline verticaltransistors which are both column adjacent and row adjacent.
 26. Thememory device of claim 24, wherein each pillar includes a capacitorcoupled to the second contact layer.
 27. The memory device of claim 24,wherein each single crystalline vertical body region has a verticallength of less than 100 nanometers.
 28. The memory device of claim 22,wherein each single crystalline vertical transistors has a verticallength of less than 100 nanometers and a horizontal width of less than10 nanometers.
 29. The memory device of claim 22, wherein each of theplurality of word lines includes a horizontally oriented word linehaving a vertical side of less than 100 nanometers opposing the singlecrystalline vertical body regions.
 30. The memory device of claim 22,wherein each of the plurality of word lines includes a verticallyoriented word line having a vertical length of less than 100 nanometersopposing the single crystalline vertical body regions.
 31. An open bitline DRAM device, comprising: an array of memory cells, wherein eachmemory cell in the array of memory cells includes: a pillar extendingoutwardly from a semiconductor substrate, wherein the pillar includes asingle crystalline first contact layer and a single crystalline secondcontact layer separated by an oxide layer; a pair of single crystallinevertical transistors formed along opposing sides of each pillar, whereineach single crystalline vertical transistor includes; an ultra thinsingle crystalline vertical first source/drain region coupled to thefirst contact layer; an ultra thin single crystalline vertical secondsource/drain region coupled to the second contact layer; an ultra thinsingle crystalline vertical body region formed along side of the oxidelayer and which couples the first and the second source/drain regions;and a gate opposing the vertical body region and separated therefrom bya gate oxide; a plurality of buried bit lines formed of singlecrystalline semiconductor material and disposed below the pillars in thearray memory cells for interconnecting with the first contact layer ofcolumn adjacent pillars in the array of memory cells; and a plurality offirst word lines, each first word line disposed orthogonally to theplurality of buried bit lines in a trench between rows of the pillarsfor addressing gates of the single crystalline vertical transistors thatare adjacent to a first side of the trench; and a plurality of secondword lines, each second word line disposed orthogonally to the bit linesin the trench between rows of the pillars and separated from each firstword line by an insulator such that the second wordline is adjacent asecond side of the trench and addresses gates of the single crystallinevertical transistors that are adjacent to a second side of the trench.32. The open bit line DRAM device of claim 31, wherein each gate along arow of pillars adjacent a first side of the trench is integrally formedwith one of the plurality of the first word lines adjacent the firstside of the trench, and wherein each gate along a row of pillarsadjacent a second side of the trench is integrally formed with one ofthe plurality of the second word lines adjacent the second side of thetrench.
 33. The open bit line DRAM device of claim 32, wherein each ofthe plurality of first and second word lines includes a verticallyoriented word line having a vertical length of less than 100 nanometers.34. The open bit line DRAM device of claim 31, wherein each singlecrystalline vertical transistors has a vertical length of less than 100nanometers and a horizontal width of less than 10 nanometers.
 35. Anelectronic system, comprising: a processor; and an open bit line DRAMdevice coupled to the processor, wherein the open bit line DRAM deviceincludes: an array of memory cells, wherein each memory cell in thearray of memory cells includes: a pillar extending outwardly from asemiconductor substrate, wherein the pillar includes a singlecrystalline first contact layer and a single crystalline second contactlayer separated by an oxide layer; a single crystalline verticaltransistor formed along side of the pillar having a vertical length ofless than 100 nanometers and a horizontal width of less than 10nanometers, wherein the single crystalline vertical transistor includes;an ultra thin single crystalline vertical first source/drain regioncoupled to the first contact layer; an ultra thin single crystallinevertical second source/drain region coupled to the second contact layer;an ultra thin single crystalline vertical body region formed along sideof the oxide layer and which couples the first and the secondsource/drain regions; and a gate opposing the vertical body region andseparated therefrom by a gate oxide; a plurality of buried bit linesformed of single crystalline semiconductor material and disposed belowthe pillars in the array memory cells for interconnecting with the firstcontact layer of column adjacent pillars in the array of memory cells;and a plurality of word lines, each word line disposed orthogonally tothe plurality of buried bit lines in a trench between rows of thepillars for addressing gates of the single crystalline verticaltransistors that are adjacent to the trench.
 36. A method for forming atransistor, comprising: forming a pillar extending outwardly from asemiconductor substrate, wherein forming the pillar includes forming asingle crystalline first contact layer of a first conductivity type andforming a single crystalline second contact layer of the firstconductivity type vertically separated by an oxide layer; forming asingle crystalline vertical transistor along side of the pillar, whereinforming the single crystalline vertical transistor includes: depositinga lightly doped polysilicon layer of a second conductivity type over thepillar and directionally etching the polysilicon layer of the secondconductivity type to leave only on sidewalls of the pillars; annealingthe pillar such that the lightly doped polysilicon layer of the secondconductivity type recrystallizes and lateral epitaxial solid phaseregrowth occurs vertically to form a single crystalline verticallyoriented material of the second conductivity type; and wherein theannealing causes the single crystalline first and second contact layersof a first conductivity type seed a growth of single crystallinematerial of the first conductivity type into the lightly dopedpolysilicon layer of the second type to form vertically oriented firstand second source/drain regions of the first conductivity type separatedby the now single crystalline vertically oriented material of the secondconductivity type; and forming a gate opposing the single crystallinevertically oriented material of the second conductivity type.
 37. Themethod of claim 36, wherein forming a single crystalline verticaltransistor along side of the pillar includes forming the transistor suchthat the transistor has an ultra thin single crystalline vertical bodyregion having a horizontal width of less than 10 nanometers.
 38. Themethod of claim 36, wherein forming a single crystalline verticaltransistor along side of the pillar includes forming the transistor suchthat the transistor has a vertical channel length of less than 100nanometers and has a first and a second source/drain regions wherein thefirst and the second source/drain regions have a horizontal width ofless than 10 nanometers.
 39. A method for forming a memory cell,comprising: forming a pillar extending outwardly from a semiconductorsubstrate, wherein forming the pillar includes forming a singlecrystalline first contact layer of a first conductivity type and forminga single crystalline second contact layer of the first conductivity typevertically separated by an oxide layer; forming a single crystallinevertical transistor along side of the pillar, wherein forming the singlecrystalline vertical transistor includes: depositing a lightly dopedpolysilicon layer of a second conductivity type over the pillar anddirectionally etching the polysilicon layer of the second conductivitytype to leave only on sidewalls of the pillars; annealing the pillarsuch that the lightly doped polysilicon layer of the second conductivitytype recrystallizes and lateral epitaxial solid phase regrowth occursvertically to form a single crystalline vertically oriented material ofthe second conductivity type; and wherein the annealing causes thesingle crystalline first and second contact layers of a firstconductivity type seed a growth of single crystalline material of thefirst conductivity type into the lightly doped polysilicon layer of thesecond type to form vertically oriented first and second source/drainregions of the first conductivity type separated by the now singlecrystalline vertically oriented material of the second conductivitytype; and forming a gate opposing the single crystalline verticallyoriented material of the second conductivity type and separatedtherefrom by a gate oxide; forming a buried bit line of singlecrystalline semiconductor material below the pillar and coupled to thefirst contact layer; forming a capacitor coupled to the second contactlayer; and forming a word line disposed orthogonally to the buried bitline in a trench below a top surface of the pillar for addressing thegate.
 40. The method of claim 39, wherein forming the buried bit lineincludes forming a buried bit line which is more heavily doped than thefirst contact layer and is formed integrally with the first contactlayer.
 41. The method of claim 39, wherein forming a single crystallinevertical transistor along side of the pillar includes forming thetransistor such that the transistor has the ultra thin singlecrystalline vertical body region with a p-type channel having a verticallength of less than 100 nanometers.
 42. The method of claim 41, whereinforming the transistor such that the transistor has the ultra thinsingle crystalline vertical body region includes forming the ultra thinsingle crystalline vertical body region to have a horizontal width ofless than 10 nanometers
 43. The method of claim 39, wherein forming aburied bit line of single crystalline semiconductor material below thepillar includes forming a buried bit line which is separated from thesemiconductor substrate by an insulator layer.
 44. The method of claim39, wherein forming the gate includes forming a horizontally orientedgate, wherein a vertical side of the horizontally oriented gate has alength of less than 100 nanometers.
 45. The method of claim 39, whereinforming the gate includes forming a vertically oriented gate having avertical length of less than 100 nanometers.
 46. A method for forming anopen bit line DRAM device, comprising: forming an array of memory cells,wherein forming each memory cell in the array of memory cells includes:forming a pillar extending outwardly from a semiconductor substrate,wherein forming the pillar includes forming a single crystalline firstcontact layer of a first conductivity type and forming a singlecrystalline second contact layer of the first conductivity typevertically separated by an oxide layer; forming a single crystallinevertical transistor along side of the pillar, wherein forming the singlecrystalline vertical transistor includes: depositing a lightly dopedpolysilicon layer of a second conductivity type over the pillar anddirectionally etching the polysilicon layer of the second conductivitytype to leave only on sidewalls of the pillars; annealing the pillarsuch that the lightly doped polysilicon layer of the second conductivitytype recrystallizes and lateral epitaxial solid phase regrowth occursvertically to form a single crystalline vertically oriented material ofthe second conductivity type; and wherein the annealing causes thesingle crystalline first and second contact layers of a firstconductivity type seed a growth of single crystalline material of thefirst conductivity type into the lightly doped polysilicon layer of thesecond type to form vertically oriented first and second source/drainregions of the first conductivity type separated by the now singlecrystalline vertically oriented material of the second conductivitytype; and forming a gate opposing the single crystalline verticallyoriented material of the second conductivity type and separatedtherefrom by a gate oxide; forming a plurality of buried bit lines ofsingle crystalline semiconductor material and disposed below the pillarsin the array memory cells such that each one of the plurality of buriedbit lines couples the first contact layer of column adjacent pillars inthe array of memory cells; and forming a plurality of word linesdisposed orthogonally to the plurality of buried bit lines, whereinforming the plurality of word lines includes forming each one of theplurality of wordlines in a trench between rows of the pillars foraddressing gates of the single crystalline vertical transistors that areadjacent to the trench.
 47. The method of claim 46, wherein forming eachsingle crystalline vertical transistor includes forming an ultra thinbody region with a p-type channel having a vertical length of less than100 nanometers and a horizontal width of less than 10 nanometers. 48.The method of claim 46, wherein forming the plurality of buried bitlines includes forming the plurality of buried bit lines separated by anoxide layer from the semiconductor substrate.
 49. The method of claim46, wherein forming the plurality of wordlines includes integrallyforming each gate along a row of pillars with one of the plurality ofword lines in the adjacent trench, and wherein forming each of theplurality of word lines includes forming a horizontally oriented wordline having a vertical side of less than 100 nanometers opposing thesingle crystalline vertical transistor.
 50. The method of claim 46,wherein forming the plurality of wordlines includes integrally formingeach gate along a row of pillars with one of the plurality of word linesin the adjacent trench, and wherein forming each of the plurality ofword lines includes forming a vertically oriented word line having avertical length of less than 100 nanometers.
 51. The method of claim 46,wherein forming the plurality of word lines includes in a trench betweenrows of the pillars for addressing gates of the single crystallinevertical transistors includes forming the plurality of word lines suchthat each word line addresses gates for the single crystalline verticaltransistors which are both column adjacent and row adjacent.
 52. Amethod of forming a memory device, comprising: forming an array ofmemory cells, wherein forming each memory cell in the array of memorycells includes: forming a pillar extending outwardly from asemiconductor substrate, wherein forming the pillar includes forming asingle crystalline first contact layer of a first conductivity type andforming a single crystalline second contact layer of the firstconductivity type vertically separated by an oxide layer; forming a pairof single crystalline vertical transistor along opposing sides of thepillar, wherein forming each one of the pair of single crystallinevertical transistors includes: depositing a lightly doped polysiliconlayer of a second conductivity type over the pillar and directionallyetching the polysilicon layer of the second conductivity type to leaveonly on opposing sidewalls of the pillars; annealing the pillar suchthat the lightly doped polysilicon layer of the second conductivity typerecrystallizes and lateral epitaxial solid phase regrowth occursvertically to form a single crystalline vertically oriented material ofthe second conductivity type; and wherein the annealing causes thesingle crystalline first and second contact layers of a firstconductivity type seed a growth of single crystalline material of thefirst conductivity type into the lightly doped polysilicon layer of thesecond type to form vertically oriented first and second source/drainregions of the first conductivity type separated by the now singlecrystalline vertically oriented material of the second conductivitytype; and forming a pair of gates, each gate opposing the singlecrystalline vertically oriented material of the second conductivity typeand separated therefrom by a gate oxide; forming a plurality of buriedbit lines of single crystalline semiconductor material and disposedbelow the pillars in the array memory cells such that each one of theplurality of buried bit lines couples the first contact layer of columnadjacent pillars in the array of memory cells; and forming a pluralityof first word lines disposed orthogonally to the plurality of buried bitlines in a trench between rows of the pillars for addressing gates ofthe single crystalline vertical transistors that are adjacent to a firstside of the trench; and forming a plurality of second word linesdisposed orthogonally to the bit lines in the trench between rows of thepillars and separated from each first word line by an insulator suchthat the second wordline is adjacent a second side of the trench andaddresses gates of the single crystalline vertical transistors that areadjacent to a second side of the trench.
 53. The method of claim 52,wherein forming the plurality of first wordlines includes integrallyforming each gate along a row of pillars adjacent a first side of thetrench with one of the plurality of the first word lines adjacent thefirst side of the trench, and wherein forming the plurality of secondwordlines includes integrally forming each gate along a row of pillarsadjacent a second side of the trench with one of the plurality of thesecond word lines adjacent the second side of the trench.
 54. The methodof claim 53, wherein forming each of the plurality of first and secondword lines includes forming vertically oriented word lines having avertical length of less than 100 nanometers.
 55. The method of claim 53,wherein forming each single crystalline vertical transistor includesforming the single crystalline vertical transistor to have a verticallength of less than 100 nanometers and a horizontal width of less than10 nanometers.